The read-out system is structured as a multichannel waveform recorder that stores the charge information collected by the sense wires during the drift of electrons. Each wire is equipped with a current integrating amplifier followed by a 10 bit Flash ADC that samples the signal every 400 ns. The converted data is stored in a digital memory for further evaluation.
To preserve the signal shape and to have, at the same time, a compact hardware structure, individual channels are grouped in sets of 16 and their signals are multiplexed at a rate of 40 MHz providing the required 400 ns sampling time for each channel.
The real-time analysis of the digitized signals is performed by the specially developed VLSI chip, called the hit finder chip or the DAEDALUS chip. It processes four groups of four channels, starting by demultiplexing the 10 bit input data. The chip architecture is a six-stage pipeline : one stage is dedicated to demultiplex inputs, one to multiplex outputs, one to perform median filtering, while the hit finder requires three stages. Data move through the pipeline at a frequency of 2.5 MHz that matches the input data rate. The chip features programmable operating parameters: median filter size (up to 15 points), window size (up to 15 counts) and all the threshold values.
The chip development started with the prototypes operating on four channels and designed in VLSI 0.7 μm CMOS standard cell technology. They performed according to the specifications. The final version of the chip has been desinged in VLSI 0.5 μm CMOS gate array technology and, as described above, it operates on a set of 16 channels.
The front-end electronics consists of three basic electronic modules, operating on sets of 32 channels: the decoupling board, the analog board and the digital board hosting two DAEDALUS chips.
The read-out scheme of the whole detector is organized in units. Each unit is made of 30 unit rack that houses one VME-like analog crate (with 18 analog modules in front and 18 decoupling boards in the backplane), one digital crate (with 18 digital modules), the relative power supplies and their control and monitor. Therefore a single unit can provide up to 576 read-out channels (18 modules of 32 channels each). In order to minimize the input capacitance due to the signal cables, the racks are positioned on top of the cryostat close to the signal feedthrough flanges (Fig 47) mounted at the end of the chimneys.
The total number of electronic channels connected to wires is 2 x 13312 per T300 module (53 248 in total for the T600).
The front-end electronics is composed of three basic modules. The first is the decoupling board (A764): it receives 32 analog signals from the wire chamber and passes to the analog board via decoupling capacitor of 4.7 nF, large compared to the input (wire + cable) capacitance (average value ~400 pF for the horizontal wires of the Induction-1 plane and ~ 200 pF for the wires at +-60o of the Induction-2 and Collection planes); it also provides biasing (up to 500 V) of each electrode via a 100 MΩ resistor and the distribution of the test signals. The decoupling board is housed in the back side of a VME-like crate that houses in front the analog boards.
The second module is the analog board (CAEN-V791): it houses the amplifiers for 32 channels, based on the proprietary analog BiCMOS VLSI (two channels per chip); it also provides 16:1 multiplexing and analog-to-digital data conversion (10 bit) at 40 MHz rate. The data are transmitted to the digital board via a serial-link cable (21 bit) connected to the front panel.
The third module is the digital board (CAEN-V789) ARIANNA; it houses in a VME crate and holds two DAEDALUS VLSI chips for hit finding and zero suppresion, mounted onto a small piggy back PCB; the board serves 32 channels and receives the digital data (multiplexed) from the cable plugged into the front panel. The data is avaible via the VME bus.